1. Field of the Invention
The present invention relates to a method for converting a gap-infested read-in clock into a gap-free read-out clock having the same number of pulses on the basis of phase-shift control (PLL) and is also directed to an arrangement for implementation of the method.
2. Description of the Prior Art
Such an arrangement is utilized in the receiving path of digital multiplexer systems since the clock of the respective sub-channel is required for the recovery of the sub-channel. It is disclosed in European Patent application No. 0 266 588 A1. In this arrangement, however, realization in an integrated circuit and, in particular, the circuit simulation, presents difficulties due to the appearance of spikes.